Technology aware design and design aware technology

Maex, K; Stucchi, M; Bamal, M; Grossar, E; Dehaencc, W; Papanikolaou, A; Miranda, M; Catthoor, F

dc.contributor.author	Maex, K	en
dc.contributor.author	Stucchi, M	en
dc.contributor.author	Bamal, M	en
dc.contributor.author	Grossar, E	en
dc.contributor.author	Dehaencc, W	en
dc.contributor.author	Papanikolaou, A	en
dc.contributor.author	Miranda, M	en
dc.contributor.author	Catthoor, F	en
dc.date.accessioned	2014-03-01T02:49:58Z
dc.date.available	2014-03-01T02:49:58Z
dc.date.issued	2005	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/34830
dc.subject	Levels of Abstraction	en
dc.subject	System Design	en
dc.title	Technology aware design and design aware technology	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ICICDT.2005.1502596	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ICICDT.2005.1502596	en
heal.publicationDate	2005	en
heal.abstract	Scaling beyond the 90nm node is not automatically accompanied by a lower energy per function and a better performance. This is true both for transistors and interconnects. Since IC performance remains important in a competitive world, the success of scaled technologies are to be coupled with innovative circuit and system design strategies. Therefore, a much higher synergy between technology and	en
heal.journalName	IEEE International Conference on Integrated Circuit Design and Technology	en
dc.identifier.doi	10.1109/ICICDT.2005.1502596	en