dc.contributor.author |
Larsen, AN |
en |
dc.contributor.author |
Kanjilal, A |
en |
dc.contributor.author |
Hansen, JL |
en |
dc.contributor.author |
Gaiduk, P |
en |
dc.contributor.author |
Normand, P |
en |
dc.contributor.author |
Dimitrakis, P |
en |
dc.contributor.author |
Tsoukalas, D |
en |
dc.contributor.author |
Cherkashin, N |
en |
dc.contributor.author |
Claverie, A |
en |
dc.date.accessioned |
2014-03-01T02:50:05Z |
|
dc.date.available |
2014-03-01T02:50:05Z |
|
dc.date.issued |
2005 |
en |
dc.identifier.issn |
02729172 |
en |
dc.identifier.uri |
https://dspace.lib.ntua.gr/xmlui/handle/123456789/34895 |
|
dc.relation.uri |
http://www.scopus.com/inward/record.url?eid=2-s2.0-20344383492&partnerID=40&md5=0e4e4ce4fcb2b44330e6351198b9403e |
en |
dc.subject.other |
Capacitance |
en |
dc.subject.other |
Electric potential |
en |
dc.subject.other |
Electric power utilization |
en |
dc.subject.other |
Electron tunneling |
en |
dc.subject.other |
Gates (transistor) |
en |
dc.subject.other |
Logic devices |
en |
dc.subject.other |
Melting |
en |
dc.subject.other |
Molecular beam epitaxy |
en |
dc.subject.other |
MOS capacitors |
en |
dc.subject.other |
MOSFET devices |
en |
dc.subject.other |
Potential energy |
en |
dc.subject.other |
Semiconducting germanium |
en |
dc.subject.other |
Silica |
en |
dc.subject.other |
Melting temperatures |
en |
dc.subject.other |
Nanocrystal size |
en |
dc.subject.other |
Rapid thermal processing (RTP) |
en |
dc.subject.other |
Spatial distribution |
en |
dc.subject.other |
Nanostructured materials |
en |
dc.title |
Ge nanocrystals in MOS-memory structures produced by molecular-beam epitaxy and rapid-thermal processing |
en |
heal.type |
conferenceItem |
en |
heal.identifier.secondary |
D6.2 |
en |
heal.publicationDate |
2005 |
en |
heal.abstract |
A method of forming a sheet of Ge nanocrystals in a SiO2 layer based on molecular beam epitaxy (MBE) and rapid thermal processing (RTF) is presented. The method takes advantage of the very high precision by which a very thin Ge layer can be deposited by MBE. With proper choice of process parameters the nanocrystal size can be varied between ∼3 and ∼8 nm and the area-density between ∼1×1011 and ∼1×10 12 dots/cm2. The tunneling oxide thickness is determined by the thickness of a thermally grown SiO2 layer, and is typically 4 nm. C-V measurements of MOS capacitors reveal hole and electron injection from the substrate into the nanocrystals. Memory windows of about 0.2 and 0.5 V for gate-voltage sweeps of 3 and 6 V, respectively, are achieved. © 2005 Materials Research Society. |
en |
heal.journalName |
Materials Research Society Symposium Proceedings |
en |
dc.identifier.volume |
830 |
en |
dc.identifier.spage |
263 |
en |
dc.identifier.epage |
267 |
en |