A high-level timing model for variability characterization of interconnect circuits

Miranda, M; Papanikolaou, A; Wang, H; Kaspiris, M; David, P; Catthoor, F

dc.contributor.author	Miranda, M	en
dc.contributor.author	Papanikolaou, A	en
dc.contributor.author	Wang, H	en
dc.contributor.author	Kaspiris, M	en
dc.contributor.author	David, P	en
dc.contributor.author	Catthoor, F	en
dc.date.accessioned	2014-03-01T02:50:14Z
dc.date.available	2014-03-01T02:50:14Z
dc.date.issued	2006	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/34977
dc.subject	Circuit Design	en
dc.subject	Logic Synthesis	en
dc.subject	Monte Carlo	en
dc.subject	Physical Design	en
dc.title	A high-level timing model for variability characterization of interconnect circuits	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/DTIS.2006.1708650	en
heal.identifier.secondary	http://dx.doi.org/10.1109/DTIS.2006.1708650	en
heal.publicationDate	2006	en
heal.abstract	At nanometer nodes (e.g., 45nm and beyond), stochastic fluctuations on the implemented features and doping levels during the processing of devices is making the electrical parameters of wires and transistors to become more unpredictable, resulting in process variability. Designers cannot neglect the impact of variability on their designs any more, not only during physical design but also during logic synthesis.	en
heal.journalName	International Conference on Design and Technology of Integrated Systems in Nanoscale Era	en
dc.identifier.doi	10.1109/DTIS.2006.1708650	en