Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations

Papanikolaou, A; Grabner, T; Miranda, M; Roussel, P; Catthoor, F

dc.contributor.author	Papanikolaou, A	en
dc.contributor.author	Grabner, T	en
dc.contributor.author	Miranda, M	en
dc.contributor.author	Roussel, P	en
dc.contributor.author	Catthoor, F	en
dc.date.accessioned	2014-03-01T02:50:17Z
dc.date.available	2014-03-01T02:50:17Z
dc.date.issued	2006	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/35028
dc.subject	Case Study	en
dc.subject	Energy Consumption	en
dc.subject	Perforation	en
dc.subject	Yield Loss	en
dc.subject	Yield Prediction	en
dc.title	Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1145/1176254.1176315	en
heal.identifier.secondary	http://dx.doi.org/10.1145/1176254.1176315	en
heal.publicationDate	2006	en
heal.abstract	Process variability has a detrimental impact on the perfor- mance of memories and other system components, which can lead to parametric yield loss at the system level due to timing violations. Conventional yield models do not allow to accurately analyze this, at least not at the system level. In this paper we propose a technique to estimate this sys- tem	en
heal.journalName	International Conference on Hardware/Software Codesign and System Synthesis	en
dc.identifier.doi	10.1145/1176254.1176315	en