Efficient signal processing using syntactic pattern recognition methods

Koulouris, A; Andronikos, T; Pavlatos, C; Dimopoulos, A; Panagopoulos, I; Papakonstantinou, G

dc.contributor.author	Koulouris, A	en
dc.contributor.author	Andronikos, T	en
dc.contributor.author	Pavlatos, C	en
dc.contributor.author	Dimopoulos, A	en
dc.contributor.author	Panagopoulos, I	en
dc.contributor.author	Papakonstantinou, G	en
dc.date.accessioned	2014-03-01T02:50:21Z
dc.date.available	2014-03-01T02:50:21Z
dc.date.issued	2006	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/35082
dc.relation.uri	http://www.scopus.com/inward/record.url?eid=2-s2.0-56549130309&partnerID=40&md5=a69d0c72ff48b50cab0f25cb0165afd0	en
dc.subject	FPGA	en
dc.subject	Signal processing	en
dc.subject	Syntactic pattern recognition	en
dc.subject.other	Applications	en
dc.subject.other	Combinatorial mathematics	en
dc.subject.other	Computer systems	en
dc.subject.other	Digital image storage	en
dc.subject.other	Feature extraction	en
dc.subject.other	Field programmable gate arrays (FPGA)	en
dc.subject.other	Hardware	en
dc.subject.other	Image processing	en
dc.subject.other	Imaging systems	en
dc.subject.other	Internet protocols	en
dc.subject.other	Linguistics	en
dc.subject.other	Multimedia systems	en
dc.subject.other	Pattern recognition	en
dc.subject.other	Query languages	en
dc.subject.other	Signal processing	en
dc.subject.other	Syntactics	en
dc.subject.other	Trees (mathematics)	en
dc.subject.other	Automated syntheses	en
dc.subject.other	Data representations	en
dc.subject.other	FPGA	en
dc.subject.other	Fundamental operations	en
dc.subject.other	Hardware architectures	en
dc.subject.other	Hardware designs	en
dc.subject.other	Hardware implementations	en
dc.subject.other	Natural languages	en
dc.subject.other	Optimal architectures	en
dc.subject.other	Orders of magnitudes	en
dc.subject.other	Parsing algorithms	en
dc.subject.other	Proposed architectures	en
dc.subject.other	Real-time applications	en
dc.subject.other	Software implementations	en
dc.subject.other	Source codes	en
dc.subject.other	Speed-up	en
dc.subject.other	Syntactic pattern recognition	en
dc.subject.other	Syntactic pattern recognitions	en
dc.subject.other	Xilinx fpga	en
dc.subject.other	Computer hardware description languages	en
dc.title	Efficient signal processing using syntactic pattern recognition methods	en
heal.type	conferenceItem	en
heal.publicationDate	2006	en
heal.abstract	This paper presents an optimal architecture for hardware implementation of Context-Free Grammar (CFG) parsers, which can be used to accelerate the performance of applications where response to real time signal processing is a crucial aspect, such as Electrocardiogram (ECG) analysis. Our architecture increases the performance by a factor of approximately two orders of magnitude compared to the pure software implementation, depending on the CFG. This speed up derives mainly from the hardware nature of the implementation, the innovative combinatorial nature of the circuit that implements the fundamental operation of the parsing algorithm and the underlying data representation. We further propose an automated synthesis tool that, given the specification of an arbitrary CFG and using the aforementioned hardware architecture in a template form, generates the HDL (Hardware Design Language) synthesizable source code of the hardware parser for the given grammar. The proposed architecture may be used for real time applications, e.g. natural languages interfaces. The generated source has been simulated for validation, synthesized and tested on a Xilinx FPGA (Field Programmable Gate Array) board.	en
heal.journalName	Proceedings of the 8th IASTED International Conference on Signal and Image Processing, SIP 2006	en
dc.identifier.spage	483	en
dc.identifier.epage	490	en