dc.contributor.author |
Papadopoulos, L |
en |
dc.contributor.author |
Soudris, D |
en |
dc.date.accessioned |
2014-03-01T02:51:00Z |
|
dc.date.available |
2014-03-01T02:51:00Z |
|
dc.date.issued |
2007 |
en |
dc.identifier.uri |
https://dspace.lib.ntua.gr/xmlui/handle/123456789/35278 |
|
dc.subject |
Complex Network |
en |
dc.subject |
Design Methodology |
en |
dc.subject |
Evaluation Metric |
en |
dc.subject |
High Performance |
en |
dc.subject |
Low Energy |
en |
dc.subject |
Multimedia Application |
en |
dc.subject |
Network On Chip |
en |
dc.title |
System-Level Application-Specific NoC Design for Network and Multimedia Applications |
en |
heal.type |
conferenceItem |
en |
heal.identifier.primary |
10.1007/978-3-540-74442-9_1 |
en |
heal.identifier.secondary |
http://dx.doi.org/10.1007/978-3-540-74442-9_1 |
en |
heal.publicationDate |
2007 |
en |
heal.abstract |
Nowadays, embedded consumer devices execute complex network and multimedia applications that require high performance and low energy consumption. For implementing complex applications on Network-on-Chips (NoCs), a design methodology is needed for performing exploration at NoC system-level, in order to select the optimal application-specific NoC architecture. The design methodology we present in this paper is based on the exploration of different |
en |
heal.journalName |
Workshop on Power and Timing Modeling, Optimization and Simulation |
en |
dc.identifier.doi |
10.1007/978-3-540-74442-9_1 |
en |