Topology exploration for energy efficient intra-tile communication

Guo, J; Papanikolaou, A; Catthoor, F

dc.contributor.author	Guo, J	en
dc.contributor.author	Papanikolaou, A	en
dc.contributor.author	Catthoor, F	en
dc.date.accessioned	2014-03-01T02:51:00Z
dc.date.available	2014-03-01T02:51:00Z
dc.date.issued	2007	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/35283
dc.subject	Architectural Style	en
dc.subject	Energy Efficient	en
dc.subject	Energy Optimization	en
dc.title	Topology exploration for energy efficient intra-tile communication	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ASPDAC.2007.357982	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ASPDAC.2007.357982	en
heal.publicationDate	2007	en
heal.abstract	With technology nodes scaling down, the energy consumed by the on-chip intra-tile interconnects is beginning to have a significant impact on the total chip energy. The energy-optimal sectioned bus (ESB) template is an energy efficient architecture style for on-chip communication between components. To achieve minimum energy operation, the netlist topology of the ESB bus should however be optimized accordingly. In	en
heal.journalName	Asia and South Pacific Design Automation Conference	en
dc.identifier.doi	10.1109/ASPDAC.2007.357982	en