Using a Linear Sectioned Bus And a Communication Processor to Reduce Energy Costs in Synchronous On-Chip Communication

Heyrman, K; Papanikolaou, A; Catthoor, F; Veelaert, P; Philips, W

dc.contributor.author	Heyrman, K	en
dc.contributor.author	Papanikolaou, A	en
dc.contributor.author	Catthoor, F	en
dc.contributor.author	Veelaert, P	en
dc.contributor.author	Philips, W	en
dc.date.accessioned	2014-03-01T02:51:00Z
dc.date.available	2014-03-01T02:51:00Z
dc.date.issued	2007	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/35286
dc.subject	Case Study	en
dc.subject	Energy Cost	en
dc.subject	Energy Optimization	en
dc.subject	Low Power	en
dc.subject	Synchronous Communication	en
dc.subject	Deep Sub Micron	en
dc.subject	System On Chip	en
dc.title	Using a Linear Sectioned Bus And a Communication Processor to Reduce Energy Costs in Synchronous On-Chip Communication	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ISSOC.2007.4427432	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ISSOC.2007.4427432	en
heal.publicationDate	2007	en
heal.abstract	The sectioned bus is an energy-optimal architecture for system-on-chip (SoC) communication, where we save energy by consequently switching off unused bus sections on a cycle-by-cycle basis. The communication processor is a paradigm for the control of such a bus by means of software. Synchronous communication takes place within the tiles of a SoC in the deep sub-micron technology domain. We	en
heal.journalName	IEEE International Symposium on System-on-Chip	en
dc.identifier.doi	10.1109/ISSOC.2007.4427432	en