A regular interconnection scheme for efficient mapping of DSP kernels into reconfigurable hardware

Xydis, S; Economakos, G; Pekmestzi, K

dc.contributor.author	Xydis, S	en
dc.contributor.author	Economakos, G	en
dc.contributor.author	Pekmestzi, K	en
dc.date.accessioned	2014-03-01T02:51:01Z
dc.date.available	2014-03-01T02:51:01Z
dc.date.issued	2007	en
dc.identifier.issn	22195491	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/35301
dc.relation.uri	http://www.scopus.com/inward/record.url?eid=2-s2.0-84863746864&partnerID=40&md5=2347cc33285156eeb58dde39be43c523	en
dc.subject.other	Coarse-grained	en
dc.subject.other	Computational resources	en
dc.subject.other	Data-paths	en
dc.subject.other	Design flows	en
dc.subject.other	Design technique	en
dc.subject.other	DSP application	en
dc.subject.other	Hardware utilization	en
dc.subject.other	Latency reduction	en
dc.subject.other	Design	en
dc.subject.other	Signal processing	en
dc.subject.other	Hardware	en
dc.title	A regular interconnection scheme for efficient mapping of DSP kernels into reconfigurable hardware	en
heal.type	conferenceItem	en
heal.publicationDate	2007	en
heal.abstract	This paper presents a design technique for coarse grained reconfigurable cores targeting mostly DSP applications. The proposed technique inlines flexibility into custom Carry-Save-Arithmetic (CSA) datapaths exploiting a stable and canonical interconnection scheme. The canonical interconnection is revealed by a uniformity transformation imposed on the basic architectures of CSA multipliers and CSA chain-adders/subtracters. The design flow for the implementation of the core is analyzed in detail, and the advanced mapping opportunities are presented. The paper concludes with the experimental results showing that our architecture performs an average latency reduction of 32.63%, compared with datapaths of primitive computational resources, with sufficient hardware utilization. © 2007 EURASIP.	en
heal.journalName	European Signal Processing Conference	en
dc.identifier.spage	1004	en
dc.identifier.epage	1008	en