High-level synthesis heuristics for run-time reconfigurable architectures

Economakos, G; Xydis, S

dc.contributor.author	Economakos, G	en
dc.contributor.author	Xydis, S	en
dc.date.accessioned	2014-03-01T02:51:06Z
dc.date.available	2014-03-01T02:51:06Z
dc.date.issued	2007	en
dc.identifier.issn	22195491	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/35366
dc.relation.uri	http://www.scopus.com/inward/record.url?eid=2-s2.0-84863750424&partnerID=40&md5=ddfc156037d10af44b013710853345f9	en
dc.subject.other	Clock cycles	en
dc.subject.other	Data paths	en
dc.subject.other	FPGA devices	en
dc.subject.other	High Level Synthesis	en
dc.subject.other	Implementation platforms	en
dc.subject.other	Partial reconfiguration	en
dc.subject.other	Programmable devices	en
dc.subject.other	Resource-constrained	en
dc.subject.other	Run time reconfiguration	en
dc.subject.other	Runtimes	en
dc.subject.other	Algorithms	en
dc.subject.other	Degradation	en
dc.subject.other	Reconfigurable architectures	en
dc.subject.other	Signal processing	en
dc.subject.other	Field programmable gate arrays (FPGA)	en
dc.title	High-level synthesis heuristics for run-time reconfigurable architectures	en
heal.type	conferenceItem	en
heal.publicationDate	2007	en
heal.abstract	High-level synthesis is becoming more popular as design densities keep increasing in both the ASIC and FPGA world. Additionally, modern programmable devices offer the advantage of partial reconfiguration, which allows an algorithm to be partially mapped into a small and fixed FPGA device that can be reconfigured at run time, as the mapped application changes its requirements. This paper presents resource constrained high-level synthesis heuristics, which utilize reconfigurable datapath components under a variety of implementation platforms. The resulting architectures can be shortened so that the gain in clock cycles outperforms the timing overhead of reconfiguration. The main advantage of the proposed methodology is that through run time reconfiguration, more complicated algorithms can be mapped into smaller devices without speed degradation. © 2007 EURASIP.	en
heal.journalName	European Signal Processing Conference	en
dc.identifier.spage	1658	en
dc.identifier.epage	1662	en