A tool flow for predicting system level timing failures due to interconnect reliability degradation

Guo, J; Papanikolaou, A; Stucchi, M; Croes, K; Tokei, Z; Catthoor, F

dc.contributor.author	Guo, J	en
dc.contributor.author	Papanikolaou, A	en
dc.contributor.author	Stucchi, M	en
dc.contributor.author	Croes, K	en
dc.contributor.author	Tokei, Z	en
dc.contributor.author	Catthoor, F	en
dc.date.accessioned	2014-03-01T02:51:18Z
dc.date.available	2014-03-01T02:51:18Z
dc.date.issued	2008	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/35464
dc.subject	System Performance	en
dc.title	A tool flow for predicting system level timing failures due to interconnect reliability degradation	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1145/1366110.1366180	en
heal.identifier.secondary	http://dx.doi.org/10.1145/1366110.1366180	en
heal.publicationDate	2008	en
heal.abstract	The continuous scaling of feature dimensions and the introduction of new dielectric materials is pushing the interconnects closer to their reliability limits. Degradation mechanisms are becoming more pronounced, making the interconnect lifetime a challenge at the level of process qualification. Moreover, these mechanisms exhibit new properties, like gradual degradation of electrical parameters instead of abrupt breakdowns phenomena. As a result,	en
heal.journalName	ACM Great Lakes Symposium on VLSI	en
dc.identifier.doi	10.1145/1366110.1366180	en