Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip

Anagnostopoulos, I; Bartzas, A; Soudris, D

dc.contributor.author	Anagnostopoulos, I	en
dc.contributor.author	Bartzas, A	en
dc.contributor.author	Soudris, D	en
dc.date.accessioned	2014-03-01T02:51:52Z
dc.date.available	2014-03-01T02:51:52Z
dc.date.issued	2009	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/35697
dc.subject	Interconnection Network	en
dc.subject	Power Consumption	en
dc.subject	Routing Algorithm	en
dc.subject	Network On Chip	en
dc.title	Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1007/978-3-642-11802-9_13	en
heal.identifier.secondary	http://dx.doi.org/10.1007/978-3-642-11802-9_13	en
heal.publicationDate	2009	en
heal.abstract	Network-on-Chip (NoC), a new SoC paradigm, has been proposed as a solution to mitigate complex on-chip interconnection problems. NoC architectures are able to accommodate a large number of IP cores in the same chip implementing a set of complex applications. Power consumption is a critical issue in interconnection network in NoC design, driven by power-related design constraints, such as thermal	en
heal.journalName	Workshop on Power and Timing Modeling, Optimization and Simulation	en
dc.identifier.doi	10.1007/978-3-642-11802-9_13	en