Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach

Candaele, B; Aguirre, S; Sarlotte, M; Anagnostopoulos, I; Xydis, S; Bartzas, A; Bekiaris, D; Soudris, D; Lu, Z; Chen, X; Chabloz, J; Hemani, A; Jantsch, A; Vanmeerbeeck, G; Kreku, J; Tiensyrjä, K; Ieromnimon, F; Kritharidis, D; Wiefrink, A; Vanthournout, B; Martin, P

dc.contributor.author	Candaele, B	en
dc.contributor.author	Aguirre, S	en
dc.contributor.author	Sarlotte, M	en
dc.contributor.author	Anagnostopoulos, I	en
dc.contributor.author	Xydis, S	en
dc.contributor.author	Bartzas, A	en
dc.contributor.author	Bekiaris, D	en
dc.contributor.author	Soudris, D	en
dc.contributor.author	Lu, Z	en
dc.contributor.author	Chen, X	en
dc.contributor.author	Chabloz, J	en
dc.contributor.author	Hemani, A	en
dc.contributor.author	Jantsch, A	en
dc.contributor.author	Vanmeerbeeck, G	en
dc.contributor.author	Kreku, J	en
dc.contributor.author	Tiensyrjä, K	en
dc.contributor.author	Ieromnimon, F	en
dc.contributor.author	Kritharidis, D	en
dc.contributor.author	Wiefrink, A	en
dc.contributor.author	Vanthournout, B	en
dc.contributor.author	Martin, P	en
dc.date.accessioned	2014-03-01T02:52:31Z
dc.date.available	2014-03-01T02:52:31Z
dc.date.issued	2010	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/35899
dc.subject	configural processing	en
dc.subject	Data Management	en
dc.subject	Data Structure	en
dc.subject	Development Tool	en
dc.subject	Distributed Memory	en
dc.subject	Energy Performance	en
dc.subject	Middleware	en
dc.subject	Parallel Systems	en
dc.subject	Power Consumption	en
dc.subject	Shared Memory	en
dc.subject	Network On Chip	en
dc.title	Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ISVLSI.2010.71	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ISVLSI.2010.71	en
heal.publicationDate	2010	en
heal.abstract	The project will address two main challenges of prevailing architectures: 1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption, 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed	en
heal.journalName	Annual Symposium on VLSI	en
dc.identifier.doi	10.1109/ISVLSI.2010.71	en