Application-specific temperature reduction systematic methodology for 2D and 3D networks-on-chip

Anagnostopoulos, I; Bartzas, A; Soudris, D

dc.contributor.author	Anagnostopoulos, I	en
dc.contributor.author	Bartzas, A	en
dc.contributor.author	Soudris, D	en
dc.date.accessioned	2014-03-01T02:52:34Z
dc.date.available	2014-03-01T02:52:34Z
dc.date.issued	2010	en
dc.identifier.issn	03029743	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/35937
dc.subject.other	3D meshes	en
dc.subject.other	3D networks	en
dc.subject.other	Application-Specific	en
dc.subject.other	Buffer sizing	en
dc.subject.other	Complex applications	en
dc.subject.other	Critical issues	en
dc.subject.other	Design constraints	en
dc.subject.other	DSP application	en
dc.subject.other	IP core	en
dc.subject.other	Network on chip	en
dc.subject.other	NoC architectures	en
dc.subject.other	NoC design	en
dc.subject.other	Novel techniques	en
dc.subject.other	On-chip interconnection	en
dc.subject.other	Peak temperatures	en
dc.subject.other	Performance penalties	en
dc.subject.other	Power Consumption	en
dc.subject.other	Power delivery	en
dc.subject.other	Power-aware routing	en
dc.subject.other	Systematic methodology	en
dc.subject.other	Temperature reduction	en
dc.subject.other	Electric power transmission	en
dc.subject.other	Interconnection networks	en
dc.subject.other	Network architecture	en
dc.subject.other	Routers	en
dc.subject.other	Technical presentations	en
dc.subject.other	Three dimensional	en
dc.subject.other	Time measurement	en
dc.subject.other	Timing circuits	en
dc.subject.other	VLSI circuits	en
dc.subject.other	Design	en
dc.title	Application-specific temperature reduction systematic methodology for 2D and 3D networks-on-chip	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1007/978-3-642-11802-9_13	en
heal.identifier.secondary	http://dx.doi.org/10.1007/978-3-642-11802-9_13	en
heal.publicationDate	2010	en
heal.abstract	Network-on-Chip (NoC), a new SoC paradigm, has been proposed as a solution to mitigate complex on-chip interconnection problems. NoC architectures are able to accommodate a large number of IP cores in the same chip implementing a set of complex applications. Power consumption is a critical issue in interconnection network in NoC design, driven by power-related design constraints, such as thermal and power delivery design. In this work, we introduce a systematic methodology for NoC temperature reduction consisting of novel techniques: i) application independent power-aware routing algorithms; and ii) application-specific platform optimizations, such as buffer sizing. The methodology achieves significant peak temperature reduction. The effectiveness of the proposed approach is evaluated both on 2D and 3D mesh topologies employing real DSP applications. A temperature reduction of 13°C and 22°C for 2D and 3D NoCs, respectively, on average, is achieved without any performance penalty. © 2010 Springer Berlin Heidelberg.	en
heal.journalName	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)	en
dc.identifier.doi	10.1007/978-3-642-11802-9_13	en
dc.identifier.volume	5953 LNCS	en
dc.identifier.spage	86	en
dc.identifier.epage	95	en