A temperature-aware time-dependent dielectric breakdown analysis framework

Bekiaris, D; Papanikolaou, A; Papameletis, C; Soudris, D; Economakos, G; Pekmestzi, K

dc.contributor.author	Bekiaris, D	en
dc.contributor.author	Papanikolaou, A	en
dc.contributor.author	Papameletis, C	en
dc.contributor.author	Soudris, D	en
dc.contributor.author	Economakos, G	en
dc.contributor.author	Pekmestzi, K	en
dc.date.accessioned	2014-03-01T02:52:51Z
dc.date.available	2014-03-01T02:52:51Z
dc.date.issued	2011	en
dc.identifier.issn	03029743	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/36111
dc.subject	Inter-Metal Dielectric Leakage	en
dc.subject	Reliability	en
dc.subject	Time-Dependent Dielectric Breakdown	en
dc.subject	Timing	en
dc.subject.other	CMOS technology	en
dc.subject.other	Complex systems	en
dc.subject.other	Critical Paths	en
dc.subject.other	Electrical characteristic	en
dc.subject.other	Inter-metal dielectrics	en
dc.subject.other	Low k dielectrics	en
dc.subject.other	SOC designs	en
dc.subject.other	System's performance	en
dc.subject.other	Technology scaling	en
dc.subject.other	Temperature variation	en
dc.subject.other	Time-Dependent Dielectric Breakdown	en
dc.subject.other	Timing	en
dc.subject.other	CMOS integrated circuits	en
dc.subject.other	Electric breakdown	en
dc.subject.other	Optimization	en
dc.subject.other	Reliability	en
dc.subject.other	Systems analysis	en
dc.subject.other	Timing circuits	en
dc.subject.other	Dielectric materials	en
dc.title	A temperature-aware time-dependent dielectric breakdown analysis framework	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1007/978-3-642-17752-1-8	en
heal.identifier.secondary	http://dx.doi.org/10.1007/978-3-642-17752-1-8	en
heal.publicationDate	2011	en
heal.abstract	The shrinking of interconnect width and thickness, due to technology scaling, along with the integration of low-k dielectrics, reveal novel reliability wear-out mechanisms, progressively affecting the performance of complex systems. These phenomena progressively deteriorate the electrical characteristics and therefore the delay of interconnects, leading to violations in timing-critical paths. This work estimates the timing impact of Time-Dependent Dielectric Breakdown (TDDB) between wires of the same layer, considering temperature variations. The proposed framework is evaluated on a Leon3 MP-SoC design, implemented at a 45nm CMOS technology. The results evaluate the system's performance drift due to TDDB, considering different physical implementation scenarios. © 2011 Springer-Verlag Berlin Heidelberg.	en
heal.journalName	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)	en
dc.identifier.doi	10.1007/978-3-642-17752-1-8	en
dc.identifier.volume	6448 LNCS	en
dc.identifier.spage	73	en
dc.identifier.epage	83	en