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Configurable baseband digital transceiver for Gbps wireless 60 GHz communications

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dc.contributor.author Diamantopoulos, D en
dc.contributor.author Galiatsatos, P en
dc.contributor.author Karachalios, A en
dc.contributor.author Lentaris, G en
dc.contributor.author Reisis, D en
dc.contributor.author Soudris, D en
dc.date.accessioned 2014-03-01T02:52:57Z
dc.date.available 2014-03-01T02:52:57Z
dc.date.issued 2011 en
dc.identifier.uri https://dspace.lib.ntua.gr/xmlui/handle/123456789/36164
dc.subject.other Base bands en
dc.subject.other Compile time en
dc.subject.other Configurable en
dc.subject.other Cutting edge technology en
dc.subject.other Digital transceivers en
dc.subject.other FPGA implementations en
dc.subject.other Low-cost devices en
dc.subject.other Maximal throughput en
dc.subject.other Parallel path en
dc.subject.other Pipelined architecture en
dc.subject.other Digital circuits en
dc.subject.other Field programmable gate arrays (FPGA) en
dc.subject.other Orthogonal frequency division multiplexing en
dc.title Configurable baseband digital transceiver for Gbps wireless 60 GHz communications en
heal.type conferenceItem en
heal.identifier.primary 10.1109/ICECS.2011.6122246 en
heal.identifier.secondary http://dx.doi.org/10.1109/ICECS.2011.6122246 en
heal.identifier.secondary 6122246 en
heal.publicationDate 2011 en
heal.abstract The evolution of 60 GHz wireless networks using Orthogonal Frequency Division Multiplexing (OFDM) technique imposed requirements of increased processing in the baseband implementations. The current paper focuses on the design of a pipelined architecture realizing the baseband functions. The design bases on using parallel paths to achieve a throughput of 1.6 Gbps. The number of paths is configured at compile time to be 4, 8 or 16, for achieving maximal throughput by either using cutting edge technology FPGA platforms or target implementations with low cost devices. FPGA implementations validate the results. © 2011 IEEE. en
heal.journalName 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011 en
dc.identifier.doi 10.1109/ICECS.2011.6122246 en
dc.identifier.spage 192 en
dc.identifier.epage 195 en


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