Design and experimentation with low-power morphable multipliers

Sotiriou-Xanthopoulos, E; Diamantopoulos, D; Economakos, G; Soudris, D

dc.contributor.author	Sotiriou-Xanthopoulos, E	en
dc.contributor.author	Diamantopoulos, D	en
dc.contributor.author	Economakos, G	en
dc.contributor.author	Soudris, D	en
dc.date.accessioned	2014-03-01T02:53:00Z
dc.date.available	2014-03-01T02:53:00Z
dc.date.issued	2011	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/36175
dc.subject.other	Building blockes	en
dc.subject.other	Coarse-grain reconfigurable	en
dc.subject.other	Connection schemes	en
dc.subject.other	Data paths	en
dc.subject.other	Digital designs	en
dc.subject.other	Hardware synthesis	en
dc.subject.other	Low Power	en
dc.subject.other	Low-power design	en
dc.subject.other	Performance improvements	en
dc.subject.other	Power gatings	en
dc.subject.other	Power improvements	en
dc.subject.other	Power overhead	en
dc.subject.other	Reconfigurable computing	en
dc.subject.other	Run time reconfiguration	en
dc.subject.other	Design	en
dc.subject.other	Experiments	en
dc.subject.other	Multiplexing	en
dc.subject.other	Multiplexing equipment	en
dc.subject.other	Multiplying circuits	en
dc.title	Design and experimentation with low-power morphable multipliers	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ICECS.2011.6122383	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ICECS.2011.6122383	en
heal.identifier.secondary	6122383	en
heal.publicationDate	2011	en
heal.abstract	Reconfigurable computing is a cost-effective alternative to technology shrinking in order to achieve higher performance in digital design, especially considering run time reconfiguration. Research in the field consists of new reconfig-urable architectures, either coarse-grain or fine-grain, and new methodologies to map applications onto them. A special case of coarse-grain reconfigurable components are morphable multipliers, which use multiplexers to feed different inputs and form different connection schemes within the datapath of conventional multipliers. These connection schemes form different components that can be utilized when the initial multiplier is idle. Morphable components offer performance improvements but the use of extra multiplexers impose power overheads. This paper applies two low-power design techniques, power gating and multi Vth components, for the design of low-power morphable multipliers. Experimentation with these multipliers show that they can offer performance, area and power improvements compared to other alternative architectures, making them valuable building blocks for hardware synthesis. © 2011 IEEE.	en
heal.journalName	2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011	en
dc.identifier.doi	10.1109/ICECS.2011.6122383	en
dc.identifier.spage	752	en
dc.identifier.epage	755	en