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Design of a 1.2-V 60 GHz transceiver in a 90nm CMOS RF technology

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dc.contributor.author Simitsakis, P en
dc.contributor.author Liolis, S en
dc.contributor.author Psyllos, D en
dc.contributor.author Mountrichas, L en
dc.contributor.author Sotiriadis, PP en
dc.date.accessioned 2014-03-01T02:53:00Z
dc.date.available 2014-03-01T02:53:00Z
dc.date.issued 2011 en
dc.identifier.uri https://dspace.lib.ntua.gr/xmlui/handle/123456789/36176
dc.subject.other 60 GHz band en
dc.subject.other 60-GHz transceivers en
dc.subject.other 90nm CMOS en
dc.subject.other Channel bandwidth en
dc.subject.other Gigabit Ethernet en
dc.subject.other Power supply en
dc.subject.other QPSK modulation en
dc.subject.other Wireless transmissions en
dc.subject.other Ethernet en
dc.subject.other Linear control systems en
dc.subject.other Power amplifiers en
dc.subject.other Quadrature phase shift keying en
dc.subject.other Transceivers en
dc.title Design of a 1.2-V 60 GHz transceiver in a 90nm CMOS RF technology en
heal.type conferenceItem en
heal.identifier.primary 10.1109/ICECS.2011.6122283 en
heal.identifier.secondary http://dx.doi.org/10.1109/ICECS.2011.6122283 en
heal.identifier.secondary 6122283 en
heal.publicationDate 2011 en
heal.abstract In this paper the design of a high-data-rate transceiver in the 60 GHz band using a QPSK modulation scheme is presented. The channel bandwidth is 1 GHz in order to achieve gigabit Ethernet wireless transmission at 1km distance. The receiver has 66 db of linear controlled gain with a noise figure of 8 dB. The transmitter is capable of delivering -12 dBm of power at the external power amplifier. Both circuits operate under a 1.2 V power supply. © 2011 IEEE. en
heal.journalName 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011 en
dc.identifier.doi 10.1109/ICECS.2011.6122283 en
dc.identifier.spage 342 en
dc.identifier.epage 345 en


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