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Performance analysis and complexity study of LDPC and turbo coding schemes for inter vehicle communications

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dc.contributor.author Kiokes, G en
dc.contributor.author Economakos, G en
dc.contributor.author Amditis, A en
dc.contributor.author Uzunoglu, NK en
dc.date.accessioned 2014-03-01T02:53:25Z
dc.date.available 2014-03-01T02:53:25Z
dc.date.issued 2011 en
dc.identifier.uri https://dspace.lib.ntua.gr/xmlui/handle/123456789/36305
dc.subject BER en
dc.subject coding en
dc.subject FPGA en
dc.subject implementation en
dc.subject LDPC en
dc.subject performance en
dc.subject Turbo en
dc.subject.other BER en
dc.subject.other coding en
dc.subject.other implementation en
dc.subject.other LDPC en
dc.subject.other performance en
dc.subject.other Turbo en
dc.subject.other Bit error rate en
dc.subject.other Coding errors en
dc.subject.other Intelligent vehicle highway systems en
dc.subject.other Mobile ad hoc networks en
dc.subject.other Quadrature phase shift keying en
dc.subject.other Rayleigh fading en
dc.subject.other Signal to noise ratio en
dc.subject.other Standards en
dc.subject.other Telecommunication networks en
dc.subject.other Turbo codes en
dc.subject.other Field programmable gate arrays (FPGA) en
dc.title Performance analysis and complexity study of LDPC and turbo coding schemes for inter vehicle communications en
heal.type conferenceItem en
heal.identifier.primary 10.1109/ITST.2011.6060119 en
heal.identifier.secondary http://dx.doi.org/10.1109/ITST.2011.6060119 en
heal.identifier.secondary 6060119 en
heal.publicationDate 2011 en
heal.abstract This paper provides a comprehensive investigation of the performance and practical implementation issues of two coding schemes, employing Turbo Codes and low-density parity-check (LDPC) codes, over vehicular ad-hoc networks based on IEEE 802.11p specifications. Using simulation authors present the results of an evaluation of system performance for the two different coding schemes. We concentrate our evaluation on two different environments AWGN and Non Line of Sight propagation environment (Rayleigh Fading). BER (Bit Error Rate) and SNR (Signal to Noise Ratio) values for QPSK modulation are examined and tested. The Forward Error Correction (FEC) system model in the transceiver with the two schemes has been implemented in a Field Programmable Gate Array (FPGA) from Xilinx. At the end, a test-bed was developed using the Nallatech XtremeDsp Development Kit with a Xilinx Virtex-4 FPGA, for comparing simulation results with real time implementations. © 2011 IEEE. en
heal.journalName 2011 11th International Conference on ITS Telecommunications, ITST 2011 en
dc.identifier.doi 10.1109/ITST.2011.6060119 en
dc.identifier.spage 559 en
dc.identifier.epage 564 en


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