Power, performance and area prediction of 3D ICs during early stage design exploration in 45nm

Toufexis, F; Papanikolaou, A; Soudris, D; Stamoulis, G; Bantas, S

dc.contributor.author	Toufexis, F	en
dc.contributor.author	Papanikolaou, A	en
dc.contributor.author	Soudris, D	en
dc.contributor.author	Stamoulis, G	en
dc.contributor.author	Bantas, S	en
dc.date.accessioned	2014-03-01T02:53:26Z
dc.date.available	2014-03-01T02:53:26Z
dc.date.issued	2011	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/36312
dc.subject.other	3-D ICs	en
dc.subject.other	Area prediction	en
dc.subject.other	Design Exploration	en
dc.subject.other	Design flows	en
dc.subject.other	Limiting factors	en
dc.subject.other	Novel design	en
dc.subject.other	Optimum system performance	en
dc.subject.other	Performance prediction	en
dc.subject.other	Power supply voltage	en
dc.subject.other	Thermal variation	en
dc.subject.other	Voltage drop	en
dc.subject.other	Drops	en
dc.subject.other	Forecasting	en
dc.subject.other	Three dimensional	en
dc.subject.other	Design	en
dc.title	Power, performance and area prediction of 3D ICs during early stage design exploration in 45nm	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ICECS.2011.6122374	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ICECS.2011.6122374	en
heal.identifier.secondary	6122374	en
heal.publicationDate	2011	en
heal.abstract	In this work, the impact of across-chip temperature and power supply voltage variations, on performance predictions in 3D ICs, is investigated. To make this possible, a novel design flow is proposed to perform design exploration of 3D ICs. Power supply voltage and thermal variations are modeled, to allow accurate PPA (power, performance and area) predictions. Using the main parts of this design flow, in a system comprising hundreds of million gates, complicated mechanisms are shown to determine the performance of the system. With increasing number of dies, timing is shown to exhibit 4 distinct regions, where either temperature or voltage drop is the dominant limiting factor. Power consumption does not scale monotonically with increasing die number. As a consequence, optimum system performance is in no way achieved by minimizing temperature and voltage drop, as is assumed in the literature so far. The across-chip temperature and power supply voltage variations are finally shown to cause on average 40% increase in timing and 53% decrease in power consumption, compared to the assumption of nominal conditions. © 2011 IEEE.	en
heal.journalName	2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011	en
dc.identifier.doi	10.1109/ICECS.2011.6122374	en
dc.identifier.spage	715	en
dc.identifier.epage	718	en