Parallel paradigms and run-time management techniques for many-core architectures: The 2PARMA approach

Silvano, C; Fornaciari, W; Reghizzi, SC; Agosta, G; Palermo, G; Zaccaria, V; Bellasi, P; Castro, F; Corbetta, S; Speziale, E; Melpignano, D; Zins, JM; Siorpaes, D; Hubert, H; Stabernack, B; Brandenburg, J; Palkovic, M; Raghavan, P; Ykman-Couvreur, C; Bartzas, A; Soudris, D; Kempf, T; Ascheid, G; Meyr, H; Ansari, J; Mahonen, P; Vanthournout, B

dc.contributor.author	Silvano, C	en
dc.contributor.author	Fornaciari, W	en
dc.contributor.author	Reghizzi, SC	en
dc.contributor.author	Agosta, G	en
dc.contributor.author	Palermo, G	en
dc.contributor.author	Zaccaria, V	en
dc.contributor.author	Bellasi, P	en
dc.contributor.author	Castro, F	en
dc.contributor.author	Corbetta, S	en
dc.contributor.author	Speziale, E	en
dc.contributor.author	Melpignano, D	en
dc.contributor.author	Zins, JM	en
dc.contributor.author	Siorpaes, D	en
dc.contributor.author	Hubert, H	en
dc.contributor.author	Stabernack, B	en
dc.contributor.author	Brandenburg, J	en
dc.contributor.author	Palkovic, M	en
dc.contributor.author	Raghavan, P	en
dc.contributor.author	Ykman-Couvreur, C	en
dc.contributor.author	Bartzas, A	en
dc.contributor.author	Soudris, D	en
dc.contributor.author	Kempf, T	en
dc.contributor.author	Ascheid, G	en
dc.contributor.author	Meyr, H	en
dc.contributor.author	Ansari, J	en
dc.contributor.author	Mahonen, P	en
dc.contributor.author	Vanthournout, B	en
dc.date.accessioned	2014-03-01T02:53:59Z
dc.date.available	2014-03-01T02:53:59Z
dc.date.issued	2012	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/36513
dc.subject	Runtime resource management, manycore architectures, Design Space Exploration, Embedded applications,	en
dc.subject.other	Amount of information	en
dc.subject.other	Bytecodes	en
dc.subject.other	Component based	en
dc.subject.other	Component-based software engineering	en
dc.subject.other	Computing architecture	en
dc.subject.other	Computing system	en
dc.subject.other	Conventional power	en
dc.subject.other	Customisation	en
dc.subject.other	Data parallelism	en
dc.subject.other	Design phase	en
dc.subject.other	Design space exploration	en
dc.subject.other	General-purpose computing	en
dc.subject.other	Hardware components	en
dc.subject.other	Hardware design	en
dc.subject.other	High performance computing	en
dc.subject.other	High-end graphics	en
dc.subject.other	Instruction set	en
dc.subject.other	Many-core	en
dc.subject.other	Many-core architecture	en
dc.subject.other	Many-core computing	en
dc.subject.other	Media processing	en
dc.subject.other	Memory mapping	en
dc.subject.other	Multi core	en
dc.subject.other	Multicore architectures	en
dc.subject.other	On chips	en
dc.subject.other	On-chip networks	en
dc.subject.other	Optimisations	en
dc.subject.other	Parallel computing system	en
dc.subject.other	Parallel programming model	en
dc.subject.other	Parallel software	en
dc.subject.other	Parallelisation	en
dc.subject.other	Parallelism extraction	en
dc.subject.other	Processing core	en
dc.subject.other	Processing units	en
dc.subject.other	Processor architectures	en
dc.subject.other	Programmability	en
dc.subject.other	Programming environment	en
dc.subject.other	Programming language	en
dc.subject.other	Programming paradigms	en
dc.subject.other	Resource management	en
dc.subject.other	Resource management policy	en
dc.subject.other	Resource management techniques	en
dc.subject.other	Resource usage	en
dc.subject.other	Runtime management	en
dc.subject.other	Runtimes	en
dc.subject.other	Scalable computing	en
dc.subject.other	Semi-automatics	en
dc.subject.other	Silicon Technologies	en
dc.subject.other	Single chips	en
dc.subject.other	Superscalar architecture	en
dc.subject.other	System reliability	en
dc.subject.other	System resources	en
dc.subject.other	Virtualisation	en
dc.subject.other	Communication	en
dc.subject.other	Computation theory	en
dc.subject.other	Computer architecture	en
dc.subject.other	Core levels	en
dc.subject.other	Design	en
dc.subject.other	Distributed computer systems	en
dc.subject.other	Embedded systems	en
dc.subject.other	Energy management	en
dc.subject.other	Industrial management	en
dc.subject.other	Interconnection networks	en
dc.subject.other	Multicore programming	en
dc.subject.other	Natural resources management	en
dc.subject.other	Network architecture	en
dc.subject.other	Optimization	en
dc.subject.other	Parallel processing systems	en
dc.subject.other	Parallel programming	en
dc.subject.other	Productivity	en
dc.subject.other	Quality of service	en
dc.subject.other	Resource allocation	en
dc.subject.other	Software engineering	en
dc.subject.other	Space research	en
dc.subject.other	Virtual reality	en
dc.subject.other	Information management	en
dc.title	Parallel paradigms and run-time management techniques for many-core architectures: The 2PARMA approach	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1145/2107763.2107774	en
heal.identifier.secondary	http://dx.doi.org/10.1145/2107763.2107774	en
heal.publicationDate	2012	en
heal.abstract	The trend in computing architectures is currently replacing complex superscalar architectures with meshes of small homogeneous processing units connected by an on-chip network. This trend is mostly driven by inherent silicon technology frontiers, which are getting as closer as the process densities levels increase. The number of cores to be integrated in a single chip is rapidly increasing in the coming years, moving from multi-core to many-core architectures. This trend requires a global rethinking of software and hardware design approaches. Multi-core architectures are nowadays prevalent in general purpose computing and in high performance computing and more scalable multi-core architectures are and will be widely adopted for high-end graphics and media processing, e.g. IBM Cell BE, NVIDIA Fermi, SUN Niagara and Tilera TILE64. The 2PARMA project focuses on the flexible family of parallel and scalable computing processors, which we call Many-core Computing Fabric (MCCF) Template, composed of many homogeneous processing cores interconnected by an on-chip mesh as shown in Figure 1. The 2PARMA project aims at providing parallel programming models and run-time resource management techniques to exploit the features of many-core processor architectures, by focusing on the definition of parallel programming models that combine component-based and single-instruction multiple-thread approaches, instruction set virtualisation based on portable bytecode, run-time resource management policies and mechanisms as well as design space exploration methodologies for Many-core Computing Fabrics. The above scientific and technical objectives are intended to meet some of the main challenges in computing system research, i.e., to improve performance by providing software programmability techniques to exploit the hardware parallelism; to provide efficient management of power/performance trade-offs through runtime resource management and optimisation; to improve system reliability, mainly in terms of lifetime and yield of hardware components by providing transparent resource reconfiguration and instruction set virtualisation; to increase the productivity of the process of developing parallel software by using semi-automatic parallelism extraction techniques and extending the OpenCL programming paradigm for parallel computing systems. The main topics investigated within the 2PARMA project are related to the analysis and development of the complete software layer able to exploit the features of future many-core processor architectures. In this context, the programmability of Many-core Computing Fabrics at both the programming language and Operating System level plays an important role. On one hand, it leverages the increasingly popular Component-Based Software Engineering (CBSE) and develops parallelism extraction techniques to identify opportunities for parallelisation in the design phase; 2PARMA then introduces extensions of existing standards for parallel programming, such as OpenCL, to express data parallelism for Many-core Computing Fabrics. On the Operating System level, 2PARMA provides the means to define and deploy peripherals to the Many-core Computing Fabric, preserving isolation among them and efficient communication between host and Computing Fabric. The 2PARMA intends providing developers with comfortable tools and programming environments aiming at increasing software cycles productivity with respect to current, mainly manual, methodologies. Given the opportunities for adaptation of the application to the available resources, 2PARMA develops intelligent policies to manage the system resources taking into account the Quality-of-Service (QoS) requirements imposed by the user to each application, while optimising the resource usage for system-wide performance and energy goals. 2PARMA project aims at supporting efficient and optimal tasks, data and devices managements, able to dynamically adapting to the changing context, while reducing as much as possible the system power consumption with respect to conventional power management strategies. Finally, continuous adaptation and runtime management require large amount of information on the system and the applications to take effective and timely decisions. 2PARMA goes beyond traditional design space exploration (DSE) by defining a methodology to provide synthetic information about the points of operation of each application with respect to the subsets of resources available. Design space exploration methodologies developed in 2PARMA provide also architectural customisation to support parallel programming models, especially communication and memory mapping. © 2012 ACM.	en
heal.journalName	ACM International Conference Proceeding Series	en
dc.identifier.doi	10.1145/2107763.2107774	en
dc.identifier.spage	39	en
dc.identifier.epage	42	en