A High Performance FPGA Implementation of a Feed-Forward Carrier Phase Recovery Algorithm for 16-QAM Real-Time Coherent Receivers

Κωσταλάμπρος, Ιωάννης - Βατίστας; Kostalampros, Ioannis - Vatistas

dc.contributor.author	Κωσταλάμπρος, Ιωάννης - Βατίστας	el
dc.contributor.author	Kostalampros, Ioannis - Vatistas	en
dc.date.accessioned	2017-10-11T10:13:58Z
dc.date.available	2017-10-11T10:13:58Z
dc.date.issued	2017-10-11
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/45748
dc.identifier.uri	http://dx.doi.org/10.26240/heal.ntua.14619
dc.rights	Αναφορά Δημιουργού - Μη Εμπορική Χρήση - Παρόμοια Διανομή 3.0 Ελλάδα	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-sa/3.0/gr/	*
dc.subject	FPGA	en
dc.subject	VHDL	en
dc.subject	Carrier-Phase-Recovery	en
dc.subject	Coherent detection	en
dc.subject	Parallel architecture	en
dc.subject	Επαναδιαμορφούμενη αρχιτεκτονική	en
dc.subject	Οπτικά συστήματα	en
dc.subject	Σύγχρονη ανίχνευση φάσης	en
dc.subject	Τηλεπικοινωνίες	en
dc.subject	Υψηλή ταχύτητα	en
dc.title	A High Performance FPGA Implementation of a Feed-Forward Carrier Phase Recovery Algorithm for 16-QAM Real-Time Coherent Receivers	en
dc.title	Υλοποίηση Αλγορίθμου Ανάκτησης Φάσης σε Αρχιτεκτονική FPGA για Υψηλής Ταχύτητας και Απόδοσης Οπτικούς Τηλεπικοινωνιακούς Δέκτες	el
dc.contributor.department	MicroLab , PCRL	el
heal.type	bachelorThesis
heal.classification	Embedded computer systems--Design and construction	en
heal.classificationURI	http://id.loc.gov/authorities/subjects/sh2008119360
heal.language	el
heal.language	en
heal.access	free
heal.recordProvider	ntua	el
heal.publicationDate	2017-07-03
heal.abstract	The majority of the modern high speed (exceeding 100Gbps) fiber-optic networks utilize both high throughput and higher order modulation schemes to cope with the bandwidth hungry modern telecommunication needs. A key enabler of such systems is coherent detection and at the heart of a coherent detection receiver lies the Carrier Recovery sub-module. While the bandwidth efficiency increases a lot with higher constellations usage (16-QAM, 64- QAM, 256-QAM etc) the noise tolerance of the link becomes even more critical and Carrier Recovery requires state-of-the-art hardware solutions. Unlike in wireless communications where the Carrier Recovery is accomplished with Digital Phase Locked Loops (PLL) in high speed optical networks there is the need of high-performance and high-parallelism hardware to keep up with the increased speeds and overcome the barrier of the limited CMOS circuit speeds. The current thesis aims at implementing a high efficiency, feed-forward Carrier Phase Recovery algorithm on an FPGA platform, targeted at 16-QAM real-time Digital Coherent Receivers. The highly-efficient FPGA platforms give us the opportunity to boost up the speed of our design by supporting an big external parallelization order. In the beginning, we compare the industry benchmarks Carrier Phase Recovery algorithms (Viterbi-Viterbi, Blind Phase Search) with a less popular but highly-efficient alternative (NLS Estimator). During the comparison stage, we derive its optimal parameters (filter's type, filter's length) through simulation. To facilitate its efficient hardware implementation we perform a polynomial approximation on the core element of the algorithm. After implementing the algorithm on the FPGA platform we perform various measurements to evaluate the system's performance and efficiency. From the performance investigation we have found that the NLS Estimator algorithm can be successfully ported on the Virtex-7 Family FPGA platform and it can provide us with high throughput beyond 46 Gbaud net rate. The system also exhibits good linewidth tolerance since all of the hardware configurationswe tested presented ...... SNR penalty for 28 GBd and for linewidth between 200 kHz and 2 MHz which is a safe margin covering more than the bandwidth of modern External Cavity Lases. All things considered our system implementation can support not only the current state-of-the-art networks but also the tomorrow's bandwidth demanding ones (300Gbps +) while yielding efficient performance and increased exibility.	en
heal.advisorName	Σούντρης, Δημήτριος	el
heal.advisorName	Αβραμόπουλος, Ηρακλής	el
heal.committeeMemberName	Σούντρης, Δημήτριος	el
heal.committeeMemberName	Αβραμόπουλος, Ηρακλής	el
heal.committeeMemberName	Πεκμεστζή, Κιαμάλ	el
heal.academicPublisher	Εθνικό Μετσόβιο Πολυτεχνείο. Σχολή Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών	el
heal.academicPublisherID	ntua
heal.numberOfPages	121 σ.	el
heal.fullTextAvailability	true