heal.abstract |
The exponential scale down of the semiconductor technology has led to compelling
improvements in power, performance and cost. This rapid scale down, however,
exacerbated the unintended process fluctuations due to the difficulty in controlling
the manufacturing process. Therefore, process variability has become a challenging
issue in modern technologies, resulting in deviations of the electrical characteristics
of circuits, impacting, mainly, the reliability and performance of chips. Although,
variability does not solely occur from manufacturing, but also from fluctuations in
supply voltage and temperature, as well as natural wear out phenomena resulting
from utilization of chips, called aging effects. In addition, the aforementioned de-
viations are expected to become even more substantial in the future technology
nodes.
Consequently, the study of chip variability becomes substantial. While all com-
puting platforms divulge variability issues, Field Programmable Gate Arrays (FP-
GAs) are of particular interest due to their reconfigurable nature. This ability
enables the programming of each resource at very low level by performing the so-
called built-in-self-tests (BISTs). Exploiting this attribute, enables us to assess the
actual performance variation by deploying custom sensors across the FPGA fabric.
In this work, we focus on the study of performance variation in 16nm FinFET
FPGAs. We formulate a comprehensive assessment methodology based on the well-
established ring oscillator sensors, which are designed utilizing diverse resource and
delay characteristics. To obtain precise results and to comprehend the nature of the
variability, we decouple variability to systematic and stochastic accompanied by ad-
equate mathematical modeling of variations. Additionally, we assess the variability
under different environmental conditions, i.e., supply voltage and temperature, to
grasp and explain their effect on variability and circuit performance.
The experimental results on four Zynq XCZU7EV show up to 7.3% intra-die
variation, increasing to 9.9% for certain operating conditions. Our approach demon-
strates that logic and FPGA routing interconnect resources (including metal wires
as well as switching transistors) present different variability, slightly uncorrelated,
which highlights the necessity on the direction towards implementing more sophis-
ticated mitigation methods/tools. |
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