Fast packet classification on FPGA using RISC-V and binary search acceleration

Αρσινόη, Πνευματικού; Arsinoi, Pnevmatikou

dc.contributor.author	Αρσινόη, Πνευματικού	el
dc.contributor.author	Arsinoi, Pnevmatikou	en
dc.date.accessioned	2020-11-19T06:33:55Z
dc.date.available	2020-11-19T06:33:55Z
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/51950
dc.identifier.uri	http://dx.doi.org/10.26240/heal.ntua.19648
dc.rights	Default License
dc.subject	HW/SW σχεδίαση	el
dc.subject	HW/SW Co-design	en
dc.subject	RISC-V	en
dc.subject	FPGA	en
dc.subject	Packet classification	en
dc.subject	Hypersplit	en
dc.title	Fast packet classification on FPGA using RISC-V and binary search acceleration	en
dc.contributor.department	Τομέας Τεχνολογίας Πληροφορικής και Υπολογιστών	el
heal.type	bachelorThesis
heal.classification	Computer Systems	en
heal.classification	Information Technology	en
heal.language	en
heal.access	free
heal.recordProvider	ntua	el
heal.publicationDate	2020-03-23
heal.abstract	Performance demands in communications technology is driving research towards advanced network processors, which are able to handle huge rates of incoming packets via application-specific circuits, however, without sacrificing all of the conventional CPU flexibility. At the same time, the advent of RISC-V, an open-source ISA processor developed at UC Berkeley, is disrupting the industry and academia by opening computer architecture to a broader research community, allowing more researchers to explore architectural and implementation issues. Combining the above, the current work considers placing dedicated VHDL accelerators next to a RISC-V processor to accommodate network functions via customized HW/SW co-processing. We deal with the most common and challenging network task, that of Packet Classification, using the HyperSplit algorithm for performance measurements in our research. We extend the instruction subset RV64IAC of the RISC-V ISA with a new instruction that corresponds to the HyperSplit binary search tree operation. For our hardware design we use the rocket chip generator, creating a configuration that includes one RV64IAC RISC-V core and the ability for core-accelerator communication. We create a VHDL HyperSplit search hardware accelerator and we connect it to the main rocket chip RISC-V core using the RoCC interface. For rapid prototyping and design exploration, we implement the binary search of HyperSplit algorithm on an Xilinx Ultrascale xcku060 FPGA. Our VHDL accelerator consumes 5K LUT, 2K DFF, 0 DSP and 570 RAMB (53% of FPGA) for storing data structures with up to 381K nodes. By tuning our pipeline, we achieved fclk= 227MHz for P=5 pipeline stages. Our RISC-V utilizes 15K LUT, 7K DFF, 0 DSP and 5 RAMB and operates at 143MHz. Adding our new accelerator, the design accelerates Packet Classification task, achieving 113x faster classification than RISC-V alone, sustaining up to 25.4M packets/sec throughput (e.g., supporting routers with 8.1Gbps traffic).	en
heal.advisorName	Σούντρης, Δημήτριος	el
heal.committeeMemberName	Σούντρης, Δημήτριος	el
heal.committeeMemberName	Τσανάκας, Παναγιώτης	el
heal.committeeMemberName	Πνευματικάτος, Διονύσιος	el
heal.academicPublisher	Εθνικό Μετσόβιο Πολυτεχνείο. Σχολή Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών. Τομέας Τεχνολογίας Πληροφορικής και Υπολογιστών	el
heal.academicPublisherID	ntua
heal.numberOfPages	75 p.	en
heal.fullTextAvailability	false