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The ParalOS Framework for Heterogeneous VPUs: Scheduling, Memory Management & Application Development

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dc.contributor.author Petrongonas, Evangelos en
dc.contributor.author Πετρόγγονας, Ευάγγελος el
dc.date.accessioned 2020-12-10T10:46:56Z
dc.date.available 2020-12-10T10:46:56Z
dc.identifier.uri https://dspace.lib.ntua.gr/xmlui/handle/123456789/52453
dc.identifier.uri http://dx.doi.org/10.26240/heal.ntua.20151
dc.rights Αναφορά Δημιουργού - Μη Εμπορική Χρήση - Παρόμοια Διανομή 3.0 Ελλάδα *
dc.rights.uri http://creativecommons.org/licenses/by-nc-sa/3.0/gr/ *
dc.subject Heterogenous architectures en
dc.subject Framework en
dc.subject Scaratchpad memory management en
dc.subject Scheduling en
dc.subject Embedded systems en
dc.subject Ενσωματωμένα συστήματα el
dc.subject Διαχείριση μνήμης el
dc.subject Δρομολόγηση el
dc.title The ParalOS Framework for Heterogeneous VPUs: Scheduling, Memory Management & Application Development en
dc.contributor.department Εργαστήριο Μικροϋπολογιστών και Ψηφιακών Συστημάτων el
heal.type bachelorThesis
heal.classification Επιστήμη Υπολογιστών el
heal.classification Computer Science en
heal.language en
heal.access free
heal.recordProvider ntua el
heal.publicationDate 2020-11-03
heal.abstract Embedded systems are presented today with the challenge of a very rapidly evolving application diversity followed by increased programming and computational complexity. As Moore’s Law is reaching a, physics induced, cul-de-sac, customised heterogeneous System-on-Chip (SoC) and more specifically Vision Processing Units (VPUs) emerge as an attractive HW solution in various application domains. However, these platforms still require sophisticated monolithic SW development to provide efficient implementations. In this context, a framework for accelerating the SW development of computationally intensive applications on VPUs, while still enabling the exploitation of their full HW potential via low-level kernel optimisations is proposed in this thesis. This framework is tailored for heterogeneous architectures and integrates a dynamic task scheduler with a high-level transparent API, a novel scratchpad memory management scheme, I/O standardisation, inter-process communication (IPC) techniques, and an insightful visual profiler. The Intel Movidius Myriad family of VPUs is used as an evaluation platform employing both synthetic benchmarks and real-world applications, which vary from Convolutional Neural Networks (CNNs) to complex computer vision algorithms for Visual Based Navigation (VBN) targeting the space industry. The results are very promising, showcasing in terms of execution time, a limited ∼8% performance overhead vs manually optimised CNN programs while achieving up to 4.2x performance gain in content-dependent applications. Regarding the Scratchpad Memory usage, a reduction of up to 33% is recorded compared to well-established memory allocators and finally the IPC cost is decreased up to 6x vs the default vendor implementation. en
heal.advisorName Σούντρης, Δημήτριος el
heal.committeeMemberName Τσανάκας, Παναγιώτης el
heal.committeeMemberName Πνευματικάτος, Διονύσιος el
heal.academicPublisher Εθνικό Μετσόβιο Πολυτεχνείο. Σχολή Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών. Τομέας Τεχνολογίας Πληροφορικής και Υπολογιστών. Εργαστήριο Μικροϋπολογιστών και Ψηφιακών Συστημάτων VLSI el
heal.academicPublisherID ntua
heal.numberOfPages 143 p. en
heal.fullTextAvailability false


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Αναφορά Δημιουργού - Μη Εμπορική Χρήση - Παρόμοια Διανομή 3.0 Ελλάδα Except where otherwise noted, this item's license is described as Αναφορά Δημιουργού - Μη Εμπορική Χρήση - Παρόμοια Διανομή 3.0 Ελλάδα