Design and Evaluation of High-Order QAM Circuits using Hybrid Approximate Techniques and Arithmetic on FPGAs

Αρμενιάκος, Γεώργιος

dc.contributor.author	Αρμενιάκος, Γεώργιος
dc.date.accessioned	2021-04-09T12:15:56Z
dc.date.available	2021-04-09T12:15:56Z
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/53321
dc.identifier.uri	http://dx.doi.org/10.26240/heal.ntua.21019
dc.rights	Αναφορά Δημιουργού - Μη Εμπορική Χρήση - Παρόμοια Διανομή 3.0 Ελλάδα	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-sa/3.0/gr/	*
dc.subject	Τηλεπικοινωνίες	el
dc.subject	Αρχιτεκτονική υπολογιστών	el
dc.subject	Σχεδίαση υπολογιστικών συστημάτων	el
dc.subject	Approximate computing	en
dc.subject	FPGA	en
dc.subject	QAM Modulation	en
dc.subject	Log Likelihood Ratio	en
dc.subject	Hardware complexity	el
dc.subject	Αποδιαμόρφωση	el
dc.subject	Ψηφιακή μετάδοση	el
dc.title	Design and Evaluation of High-Order QAM Circuits using Hybrid Approximate Techniques and Arithmetic on FPGAs	en
dc.contributor.department	microlab	el
heal.type	bachelorThesis
heal.classification	Computer science and engineering	en
heal.classification	Telecommunications	en
heal.language	el
heal.language	en
heal.access	free
heal.recordProvider	ntua	el
heal.publicationDate	2020-07-29
heal.abstract	In today's digital world, telecommunication has become the foundation for communities to seamlessly connect and share information through digital processes. The implementation of critical functions and tasks of the digital telecommunication chain imposes the strict constraints of "high-performance" and "low-power". In this direction, the Field Programmable Gate Arrays (FPGAs) are considered attractive solutions, as they offer excellent performance/Watt ratio among the embedded devices. In this thesis, we target the demodulation operation, i.e., a key process in the digital communication system. More specifically, we perform an in-depth design space exploration, considering arithmetic and approximations in the computations, to design FPGA circuits with hardware description language (VHDL). Regarding the arithmetic, we consider both fixed- and floating-point. In terms of approximations, we apply bit truncation, replace the costly accurate fixed-point multiplication with inexact radix multipliers, and model the floating-point multiplication with less computational-intensive operations. For the demodulation algorithms, we examine 3 Soft Decision and 1 Hard Decision. The evaluation of the algorithms is performed in MATLAB by examining their Bit Error Rate (BER) and LLR. The implementation of the algorithms on the FPGA is generic in variable M-ary QAM and targets full-parallel architectures to provide high-throughput. Compared to the other modulation techniques, the 64-QAM Approximate LLR algorithm delivers the best trade-offs in terms of BER-resources. For this algorithm, the FPGA implementation results show that depending on the arithmetic and the approximation scheme, we deliver logic resources reduction up to 15% with a negligible difference in BER i.e., almost the same results with the full-precision algorithm. For higher order QAM, i.e., 256, the design's logic resources reduce up to 59%, saving significant FPGA resources for other components of the telecommunication system. The clock frequency varies from 357MHz to 555MHz. Finally, a comprehensive comparison among all the approximation schemes and algorithms is performed.	en
heal.advisorName	Σούντρης, Δημήτριος
heal.committeeMemberName	Σούντρης, Δημήτριος
heal.committeeMemberName	Τσανάκας, Παναγιώτης
heal.committeeMemberName	Παναγόπουλος, Δ Αθανάσιος
heal.academicPublisher	Σχολή Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών	el
heal.academicPublisherID	ntua
heal.numberOfPages	94
heal.fullTextAvailability	false