Accelerating the secure boot process in modern microcontrollers

Ηλιάδης, Θρασύβουλος; Iliadis, Thrasyvoulos

dc.contributor.author	Ηλιάδης, Θρασύβουλος	el
dc.contributor.author	Iliadis, Thrasyvoulos	en
dc.date.accessioned	2023-06-02T06:29:14Z
dc.date.available	2023-06-02T06:29:14Z
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/57786
dc.identifier.uri	http://dx.doi.org/10.26240/heal.ntua.25483
dc.rights	Default License
dc.subject	Secure Boot	en
dc.subject	Parallelism	en
dc.subject	Hashing Algorithm	en
dc.subject	Automotive	en
dc.subject	TPM	en
dc.title	Accelerating the secure boot process in modern microcontrollers	en
heal.type	bachelorThesis
heal.classification	Computer Science	en
heal.language	en
heal.access	campus
heal.recordProvider	ntua	el
heal.publicationDate	2023-03-16
heal.abstract	In modern microcontrollers, the integrity of the system is guaranteed in the secure boot process. Specifically, every piece of the software is covered by the Secure Boot mechanism and is attested to not have been tampered with (maliciously or not). The secure boot step has been implemented to shield systems from various system attacks. However, in modern microcontrollers, this step is typically slow, thus degrading the clients' quality of service, while also being very safety critical in the automotive domain (e.g., might cause severe road accidents in cars). Even though prior works have tried to improve performance of the secure boot process by proposing probabilistic verification schemes or by running the secure boot step in the background (not in the critical path), they only utilize one core of the system. In contrast, modern architectures comprise multiple cores. which so far remain idle and are not used in the secure boot step. In this work, we accelerate the verification step in the secure boot process in modern microcontrollers by leveraging all the available cores of the underlying hardware. We make two key contributions. First, we extensively characterize and evaluate various cryptographic algorithms, which are widely-used in different domains, in the verification step of the secure boot process. Second, we accelerate the secure boot process via two novel verification schemes: i) a parallel deterministic verification scheme and ii) a parallel probabilistic verification scheme. Both schemes are running on using all the available cores of the system. We evaluate our parallel verifications schemes in two use case scenarios: i) in a microcontroller manufactured by a lead company tailored for the automotive domain, and ii) the rocket RISC-V chip. We demonstrate that our deterministic parallel scheme provides 3.7x performance improvement in the verification step, and 1.4x performance improvement in the end-to-end secure boot process over the single core-baseline using 6 cores on the microcontroller designed for automotive scenarios. On the rocket RISC-V chip, our parallel deterministic and probabilistic verification schemes improve performance by 2.2x using 8 cores and by 1.8x cores using 14 cores over the single-core baseline scheme.	en
heal.advisorName	Πνευματικάτος, Διονύσης	el
heal.committeeMemberName	Κοζύρης, Νεκτάριος	el
heal.committeeMemberName	Γκούμας, Γεώργιος	el
heal.academicPublisher	Εθνικό Μετσόβιο Πολυτεχνείο. Σχολή Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών. Τομέας Τεχνολογίας Πληροφορικής και Υπολογιστών	el
heal.academicPublisherID	ntua
heal.numberOfPages	103 σ.	el
heal.fullTextAvailability	false