Electrical characterization of MOS memory devices containing metallic nanoparticles and a high-k control oxide layer

Sargentis, Ch; Giannakopoulos, K; Travlos, A; Tsamakis, D

dc.contributor.author	Sargentis, Ch	en
dc.contributor.author	Giannakopoulos, K	en
dc.contributor.author	Travlos, A	en
dc.contributor.author	Tsamakis, D	en
dc.date.accessioned	2014-03-01T01:26:17Z
dc.date.available	2014-03-01T01:26:17Z
dc.date.issued	2007	en
dc.identifier.issn	0039-6028	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/17980
dc.subject	C-V	en
dc.subject	Discharge mechanism	en
dc.subject	Floating gate memory	en
dc.subject	Metal nanoparticles	en
dc.subject	Metallic nanoparticles	en
dc.subject	Nanocrystal memory	en
dc.subject	Nonvolatile memory	en
dc.subject	Retention time	en
dc.subject.classification	Chemistry, Physical	en
dc.subject.classification	Physics, Condensed Matter	en
dc.subject.other	Current voltage characteristics	en
dc.subject.other	Electric fields	en
dc.subject.other	Electron guns	en
dc.subject.other	MOSFET devices	en
dc.subject.other	Nanocrystals	en
dc.subject.other	Nanoparticles	en
dc.subject.other	Nonvolatile storage	en
dc.subject.other	Platinum	en
dc.subject.other	Silica	en
dc.subject.other	Discharge mechanisms	en
dc.subject.other	Electron gun evaporation	en
dc.subject.other	Floating gate memory	en
dc.subject.other	Nanocrystal memory	en
dc.subject.other	Retention time	en
dc.subject.other	MOS devices	en
dc.title	Electrical characterization of MOS memory devices containing metallic nanoparticles and a high-k control oxide layer	en
heal.type	journalArticle	en
heal.identifier.primary	10.1016/j.susc.2006.11.064	en
heal.identifier.secondary	http://dx.doi.org/10.1016/j.susc.2006.11.064	en
heal.language	English	en
heal.publicationDate	2007	en
heal.abstract	We study the electrical characteristics of a MOS structure in which Pt nanoparticles are embedded. This structure has a tunneling oxide of 3.5 nm in thickness (a SiO2 thermal oxide layer) on top of a Si wafer, and a control oxide of 27 nm (HfO2 layer deposited by electron gun evaporation). The nanoparticles are deposited on the SiO2, layer with electron gun evaporation, at room temperature. The electrical study of the structures demonstrates that the "write" process is initiated at low electric fields. This indicates that this type of memory structure can be very promising for the fabrication of high speed MOSFET memory devices with low power consumption. Our charge retention measurements also show promising results. (c) 2006 Elsevier B. V. All rights reserved.	en
heal.publisher	ELSEVIER SCIENCE BV	en
heal.journalName	Surface Science	en
dc.identifier.doi	10.1016/j.susc.2006.11.064	en
dc.identifier.isi	ISI:000248030100068	en
dc.identifier.volume	601	en
dc.identifier.issue	13	en
dc.identifier.spage	2859	en
dc.identifier.epage	2863	en