Pipelined scheduling of tiled nested loops onto clusters of SMPs using memory mapped network interfaces

Athanasaki, M; Sotiropoulos, A; Tsoukalas, G; Koziris, N

dc.contributor.author	Athanasaki, M	en
dc.contributor.author	Sotiropoulos, A	en
dc.contributor.author	Tsoukalas, G	en
dc.contributor.author	Koziris, N	en
dc.date.accessioned	2014-03-01T02:42:08Z
dc.date.available	2014-03-01T02:42:08Z
dc.date.issued	2002	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/30813
dc.subject	Experimental Evaluation	en
dc.subject	Low Latency	en
dc.subject	Nested Loops	en
dc.subject	Network Interface	en
dc.title	Pipelined scheduling of tiled nested loops onto clusters of SMPs using memory mapped network interfaces	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1145/762761.762769	en
heal.identifier.secondary	http://dx.doi.org/10.1145/762761.762769	en
heal.publicationDate	2002	en
heal.abstract	This paper describes the performance benefits attained using enhanced network interfaces to achieve low latency communication. We present a novel, pipelined scheduling approach which takes advantage of DMA communication mode, to send data to other nodes, while the CPUs are performing calculations. We also use zero-copy communication through pinned-down physical memory regions, provided by NIC's driver modules. Our testbed concerns	en
heal.journalName	Supercomputing Conference	en
dc.identifier.doi	10.1145/762761.762769	en