Efficient Field P ocessing Cores in an Innovative Protocol Processo System-on-Chip

Lykakis, G; Mouratidis, N; Vlachos, K; Nikolaou, N; Perissakis, S; Sourdis, G; Konstantoulakis, G; Pnevmatikatos, D; Reisis, D

dc.contributor.author	Lykakis, G	en
dc.contributor.author	Mouratidis, N	en
dc.contributor.author	Vlachos, K	en
dc.contributor.author	Nikolaou, N	en
dc.contributor.author	Perissakis, S	en
dc.contributor.author	Sourdis, G	en
dc.contributor.author	Konstantoulakis, G	en
dc.contributor.author	Pnevmatikatos, D	en
dc.contributor.author	Reisis, D	en
dc.date.accessioned	2014-03-01T02:42:15Z
dc.date.available	2014-03-01T02:42:15Z
dc.date.issued	2003	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/30887
dc.subject	Complex Data	en
dc.subject	Best Effort	en
dc.subject	System On Chip	en
dc.title	Efficient Field P ocessing Cores in an Innovative Protocol Processo System-on-Chip	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/DATE.2003.1186665	en
heal.identifier.secondary	http://dx.doi.org/10.1109/DATE.2003.1186665	en
heal.publicationDate	2003	en
heal.abstract	We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a System-on-Chip that integrates variable size packet buffering, specialised cores for header and field processing, generic RISC cores and scheduling blocks. We focus on the main innovation, the reprogrammable pipeline module, and discuss its internal architecture, optimised	en
heal.journalName	Design, Automation, and Test in Europe	en
dc.identifier.doi	10.1109/DATE.2003.1186665	en