A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement

Wang, H; Papanikolaou, A; Miranda, M; Catthoor, F

dc.contributor.author	Wang, H	en
dc.contributor.author	Papanikolaou, A	en
dc.contributor.author	Miranda, M	en
dc.contributor.author	Catthoor, F	en
dc.date.accessioned	2014-03-01T02:42:23Z
dc.date.available	2014-03-01T02:42:23Z
dc.date.issued	2004	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/30980
dc.subject	Physical Design	en
dc.subject	Power Consumption	en
dc.subject	Power Optimization	en
dc.subject	Power Reduction	en
dc.subject	Switching Activity	en
dc.title	A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1145/1015090.1015294	en
heal.identifier.secondary	http://dx.doi.org/10.1145/1015090.1015294	en
heal.publicationDate	2004	en
heal.abstract	This paper presents a methodology which can substantially reduce the bus power consumption in memory dominated systems. It systematically combines an activity driven placement of the memories and a bus segmentation approach for the interconnect to localize the wire switching activity and minimize the associated wire capacitive load of the memory bus. A factor of 2.8 in bus power reduction	en
heal.journalName	Asia and South Pacific Design Automation Conference	en
dc.identifier.doi	10.1145/1015090.1015294	en