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High-level synthesis methodologies for delay-area optimized coarse-grained reconfigurable coprocessor architectures
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High-level synthesis methodologies for delay-area optimized coarse-grained reconfigurable coprocessor architectures
Xydis, S
;
Pekmestzi, K
;
Soudris, D
;
Economakos, G
URI:
https://dspace.lib.ntua.gr/xmlui/handle/123456789/32876
Date:
2010
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