A heterogeneous multicore system on chip with run-time reconfigurable virtual FPGA architecture

Hubner, M; Figuli, P; Girardey, R; Soudris, D; Siozios, K; Becker, J

dc.contributor.author	Hubner, M	en
dc.contributor.author	Figuli, P	en
dc.contributor.author	Girardey, R	en
dc.contributor.author	Soudris, D	en
dc.contributor.author	Siozios, K	en
dc.contributor.author	Becker, J	en
dc.date.accessioned	2014-03-01T02:47:14Z
dc.date.available	2014-03-01T02:47:14Z
dc.date.issued	2011	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/33025
dc.subject	Dynamic and partial reconfiguration	en
dc.subject	FPGA	en
dc.subject	Heterogeneous co-design platform	en
dc.subject	Virtualization	en
dc.subject.other	AMBA bus	en
dc.subject.other	Co-designs	en
dc.subject.other	Dynamic and partial reconfiguration	en
dc.subject.other	Dynamic reconfigurability	en
dc.subject.other	Embedded application	en
dc.subject.other	FPGA architectures	en
dc.subject.other	FPGA devices	en
dc.subject.other	Hardware blocks	en
dc.subject.other	Hardware platform	en
dc.subject.other	Heterogeneous multicore	en
dc.subject.other	Heterogeneous platforms	en
dc.subject.other	Heterogeneous systems	en
dc.subject.other	Low Power	en
dc.subject.other	Lower-power consumption	en
dc.subject.other	Multi core	en
dc.subject.other	Optimized application	en
dc.subject.other	Parallel processing	en
dc.subject.other	Run-time reconfigurable	en
dc.subject.other	Target hardware	en
dc.subject.other	Virtualizations	en
dc.subject.other	Computer hardware	en
dc.subject.other	Distributed parameter networks	en
dc.subject.other	Dynamics	en
dc.subject.other	Electron beam lithography	en
dc.subject.other	Embedded systems	en
dc.subject.other	Field programmable gate arrays (FPGA)	en
dc.subject.other	Hardware	en
dc.subject.other	Profitability	en
dc.subject.other	Systems analysis	en
dc.subject.other	Virtual reality	en
dc.subject.other	Reconfigurable hardware	en
dc.title	A heterogeneous multicore system on chip with run-time reconfigurable virtual FPGA architecture	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/IPDPS.2011.135	en
heal.identifier.secondary	6008830	en
heal.identifier.secondary	http://dx.doi.org/10.1109/IPDPS.2011.135	en
heal.publicationDate	2011	en
heal.abstract	System design, especially for low power embedded applications often profit from a heterogeneous target hardware platform. The application can be partitioned into modules with specific requirements e.g. parallelism or performance in relation to the provided hardware blocks on the multicore hardware. The result is an optimized application mapping and a parallel processing with lower power consumption on the different cores on the hardware. This paper presents a heterogeneous platform consisting of a microprocessor and a field programmable gate array (FPGA) connected via a standard AMBA bus. The novelty of this approach is that the FPGA is realized as virtual reconfigurable hardware upon a traditional off the shelf FPGA device. The advantage with this approach is that the specification of the virtual FPGA stays unchanged, independent to the underlying hardware and provides therefore features, which the exploited physical host FPGA cannot provide. A special feature of the presented virtual FPGA amongst others is the dynamic reconfigurability which is for example not available with all off the shelf FPGAs. Furthermore the concept of FPGA virtualization enables the re-use of hardware blocks on other physical FPGA devices. This paper presents the hardware platform and describes the tool chain for the heterogeneous system on chip. © 2011 IEEE.	en
heal.journalName	IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum	en
dc.identifier.doi	10.1109/IPDPS.2011.135	en
dc.identifier.spage	143	en
dc.identifier.epage	149	en