Enhancing the Performance of Tiled Loop Execution onto Clusters Using Memory Mapped Network Interfaces and Pipelined Schedules

Sotiropoulos, A; Tsoukalas, G; Koziris, N

dc.contributor.author	Sotiropoulos, A	en
dc.contributor.author	Tsoukalas, G	en
dc.contributor.author	Koziris, N	en
dc.date.accessioned	2014-03-01T02:49:09Z
dc.date.available	2014-03-01T02:49:09Z
dc.date.issued	2002	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/34347
dc.subject	Low Latency	en
dc.subject	Nested Loops	en
dc.subject	Network Interface	en
dc.subject	Pc Cluster	en
dc.title	Enhancing the Performance of Tiled Loop Execution onto Clusters Using Memory Mapped Network Interfaces and Pipelined Schedules	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/IPDPS.2002.1016567	en
heal.identifier.secondary	http://dx.doi.org/10.1109/IPDPS.2002.1016567	en
heal.publicationDate	2002	en
heal.abstract	This paper describes the performance benefits attained using enhanced network interfaces to achieve low latency communication. Our experimental testbed concerns the parallel execution of tiled nested loops onto a Linux PC cluster with PCI-SCI NICs (Dolphin D330). Tiles are nec- essarily exchanging data and should also have large com- putational grain, so that their parallel execution becomes beneficial. We schedule	en
heal.journalName	International Parallel and Distributed Processing Symposium/International Parallel Processing Symposium	en
dc.identifier.doi	10.1109/IPDPS.2002.1016567	en