Comparison of a BSIM3V3 and EKV MOST Model for a 0.5um CMOS Process and Implications for Analog Circuit Design

Terry, SC; Rochelle, JM; Binkley, DM; Blalock, BJ; Foty, DP; Bucher, M

dc.contributor.author	Terry, SC	en
dc.contributor.author	Rochelle, JM	en
dc.contributor.author	Binkley, DM	en
dc.contributor.author	Blalock, BJ	en
dc.contributor.author	Foty, DP	en
dc.contributor.author	Bucher, M	en
dc.date.accessioned	2014-03-01T02:49:13Z
dc.date.available	2014-03-01T02:49:13Z
dc.date.issued	2002	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/34415
dc.relation.uri	http://www.scopus.com/inward/record.url?eid=2-s2.0-0142148177&partnerID=40&md5=d7503fcc3394c1b1fce4db9f50c120bb	en
dc.subject.other	Electric conductance	en
dc.subject.other	Electric potential	en
dc.subject.other	Integrated circuit layout	en
dc.subject.other	Transconductance	en
dc.subject.other	Analog circuits	en
dc.subject.other	CMOS integrated circuits	en
dc.title	Comparison of a BSIM3V3 and EKV MOST Model for a 0.5um CMOS Process and Implications for Analog Circuit Design	en
heal.type	conferenceItem	en
heal.publicationDate	2002	en
heal.abstract	A BSIM3V3 and EKV model for a standard 0.5 um CMOS process has been evaluated for analog applications. Critical small-signal parameters including output conductance and transconductance efficiency were simulated for devices with gate lengths ranging from 0.5 um to 33 um. In addition, the small-signal parameters were measured on test devices with similar dimensions. The results highlight the difficulty of obtaining a model that accurately predicts the operation of low voltage analog circuits.	en
heal.journalName	IEEE Nuclear Science Symposium and Medical Imaging Conference	en
dc.identifier.volume	1	en
dc.identifier.spage	317	en
dc.identifier.epage	321	en