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Comparison of a BSIM3V3 and EKV MOST Model for a 0.5um CMOS Process and Implications for Analog Circuit Design

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Comparison of a BSIM3V3 and EKV MOST Model for a 0.5um CMOS Process and Implications for Analog Circuit Design

Terry, SC; Rochelle, JM; Binkley, DM; Blalock, BJ; Foty, DP; Bucher, M
URI: https://dspace.lib.ntua.gr/xmlui/handle/123456789/34415
Date: 2002

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