Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture

Guo, J; Papanikolaou, A; Marchal, P; Catthoor, F

dc.contributor.author	Guo, J	en
dc.contributor.author	Papanikolaou, A	en
dc.contributor.author	Marchal, P	en
dc.contributor.author	Catthoor, F	en
dc.date.accessioned	2014-03-01T02:50:15Z
dc.date.available	2014-03-01T02:50:15Z
dc.date.issued	2006	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/34995
dc.subject	Energy Optimization	en
dc.subject	Indexing Terms	en
dc.subject	Intellectual Property	en
dc.subject	Optimal Solution	en
dc.subject	Physical Design	en
dc.subject	Macro Block	en
dc.subject	System On Chip	en
dc.title	Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1145/1117278.1117294	en
heal.identifier.secondary	http://dx.doi.org/10.1145/1117278.1117294	en
heal.publicationDate	2006	en
heal.abstract	The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) archi- tectural template have led to the wide utilization of reusable hard Intellectual Property (IP) cores. Macro block-based physical de- sign implementation needs to find a well balanced solution among chip area, on-chip communication energy and critical commu- nication path delay. We present in this paper	en
heal.journalName	System-Level Interconnect Prediction	en
dc.identifier.doi	10.1145/1117278.1117294	en