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Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture

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Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture

Guo, J; Papanikolaou, A; Marchal, P; Catthoor, F
URI: https://dspace.lib.ntua.gr/xmlui/handle/123456789/34995
Date: 2006

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