Implications of assembly sequences on yield and costs 3D-CSP modules

George, K; Michael, F; Reiner, G; John, S

dc.contributor.author	George, K	en
dc.contributor.author	Michael, F	en
dc.contributor.author	Reiner, G	en
dc.contributor.author	John, S	en
dc.date.accessioned	2014-03-01T02:51:06Z
dc.date.available	2014-03-01T02:51:06Z
dc.date.issued	2007	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/35368
dc.subject.other	Model parameters	en
dc.subject.other	Chip scale packages	en
dc.subject.other	Mathematical models	en
dc.subject.other	Parameter estimation	en
dc.subject.other	Sensitivity analysis	en
dc.subject.other	Microprocessor chips	en
dc.title	Implications of assembly sequences on yield and costs 3D-CSP modules	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ESTC.2006.280112	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ESTC.2006.280112	en
heal.identifier.secondary	4060837	en
heal.publicationDate	2007	en
heal.abstract	In this paper we present an analytical model for the calculation of cost and yield of incrementally assembled 3D-stacked multi-chip modules. We adopt generic cost and yield estimation models, investigate alternative building techniques and assess the sensitivity of the various model parameters, including yield per building step, availability of known good dies and testing per building step. We apply the model for the estimation of cost of a complex 3D System in Package based on the RMPD 3D-CSP® technology. © 2006 IEEE.	en
heal.journalName	ESTC 2006 - 1st Electronics Systemintegration Technology Conference	en
dc.identifier.doi	10.1109/ESTC.2006.280112	en
dc.identifier.volume	2	en
dc.identifier.spage	860	en
dc.identifier.epage	866	en