A column parity based fault detection mechanism for FIFO buffers

Sideris, I; Pekmestzi, K

dc.contributor.author	Sideris, I	en
dc.contributor.author	Pekmestzi, K	en
dc.date.accessioned	2014-03-01T11:46:38Z
dc.date.available	2014-03-01T11:46:38Z
dc.date.issued	2012	en
dc.identifier.issn	01679260	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/37985
dc.subject	Column parity	en
dc.subject	Dynamic verification	en
dc.subject	Fault detection	en
dc.subject	FIFO	en
dc.subject	Reliability	en
dc.title	A column parity based fault detection mechanism for FIFO buffers	en
heal.type	other	en
heal.identifier.primary	10.1016/j.vlsi.2012.03.004	en
heal.identifier.secondary	http://dx.doi.org/10.1016/j.vlsi.2012.03.004	en
heal.publicationDate	2012	en
heal.abstract	This paper presents a low cost fault detection mechanism for FIFO buffers. The scheme is based on column parity maintenance in a single register, which is updated by monitoring the values written to and read from the FIFO memory array. A non-zero column parity when the FIFO is empty, constitutes an indication of fault, and this property is exploited for fault detection. The technique has gains in area, power and critical path delay, at the expense of (1) greater detection latency, due to the need for the FIFO to become empty in order to assert a violation and (2) worse Silent Data Corruption (SDC) rate. © 2012 Elsevier B.V. All rights reserved.	en
heal.journalName	Integration, the VLSI Journal	en
dc.identifier.doi	10.1016/j.vlsi.2012.03.004	en