Framework for performing rapid evaluation of 3D SoCs

Diamantopoulos, D; Siozios, K; Soudris, D

dc.contributor.author	Diamantopoulos, D	en
dc.contributor.author	Siozios, K	en
dc.contributor.author	Soudris, D	en
dc.date.accessioned	2014-03-01T11:46:59Z
dc.date.available	2014-03-01T11:46:59Z
dc.date.issued	2012	en
dc.identifier.issn	00135194	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/38051
dc.subject	3D stacking	en
dc.subject	Lower-power consumption	en
dc.subject	Physical-design tools	en
dc.subject	Semiconductor technology	en
dc.title	Framework for performing rapid evaluation of 3D SoCs	en
heal.type	other	en
heal.identifier.primary	10.1049/el.2012.1321	en
heal.identifier.secondary	http://dx.doi.org/10.1049/el.2012.1321	en
heal.publicationDate	2012	en
heal.abstract	Integrating more functionality in a smaller form factor with lower power consumption pushes traditional semiconductor technology scaling to its limits. Three-dimensional (3D) chip stacking is touted as the silver bullet technology that can keep Moore's momentum and fuel the next wave of consumer electronic products. Introduced is a framework that enables rapid evaluation of 3D SoCs with existing physical design tools. © 2012 The Institution of Engineering and Technology.	en
heal.journalName	Electronics Letters	en
dc.identifier.doi	10.1049/el.2012.1321	en
dc.identifier.volume	48	en
dc.identifier.issue	12	en
dc.identifier.spage	679	en
dc.identifier.epage	681	en